74LS112
Overview
19.20 20.00 Max 16 9 7.40 Max 6.30 Unit: mm 1 1.3 1.11 Max 8 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) + 0...
| Part | 74LS112 |
|---|---|
| Description | Dual J-K Negative-edge-triggered Flip-Flops |
| Manufacturer | Hitachi Semiconductor |
| Size | 76.76 KB |
Related Datasheets
| Part Number | Manufacturer | Description |
|---|---|---|
| 74LS112A | Motorola Semiconductor | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
| 74LS112A | Fairchild Semiconductor | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
| 74LS11 | Fairchild Semiconductor | Triple 3-Input AND Gate |
| 74LS114A | Motorola Semiconductor | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |