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HD74CDCV857 - 2.5-V Phase-lock Loop Clock Driver

Description

The HD74CDCV857 is a high-performance, low-skew, low-jitter, phase locked loop clock driver.

It is specifically designed for use with DDR (Double Data Rate) synchronous DRAMs.

Features

  • Supports 60 MHz to 200 MHz operation range.
  • Distributes one differential clock input pair to ten differential clock outputs pairs.
  • Supports spread spectrum clock requirements meeting the PC100 SDRAM registered DIMM specification.
  • External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input.
  • Supports 2.5V analog supply voltage (AVCC), and 2.5 V VDDQ.
  • No external RC network required.
  • Sleep mode detection.

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Other Datasheets by Hitachi Semiconductor (now Renesas)

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HD74CDCV857 2.5-V Phase-lock Loop Clock Driver ADE-205-335C (Z) Preliminary 4th Edition March 2000 Description The HD74CDCV857 is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is specifically designed for use with DDR (Double Data Rate) synchronous DRAMs. Features • Supports 60 MHz to 200 MHz operation range • Distributes one differential clock input pair to ten differential clock outputs pairs • Supports spread spectrum clock requirements meeting the PC100 SDRAM registered DIMM specification • External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input • Supports 2.5V analog supply voltage (AVCC), and 2.
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