HD74HC533
Description
When the latch enable input is high, the Q outputs of HD74HC373 will follow the D inputs and the Q outputs of HD74HC533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.
Features
- High Speed Operation: tpd (D to Q) = 16 ns typ (CL = 50 p F)
- High Output Current: Fanout of 15 LSTTL Loads
- Wide Operating Voltage: VCC = 2 to 6 V
- Low Input Current: 1 µA max
- Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
- Ordering Information
Part Name
Package Type
Package Code (Previous Code)
Package Abbreviation
HD74HC373P HD74HC533P
DILP-20 pin
PRDP0020AC-B (DP-20NEV)
HD74HC373FPEL HD74HC533FPEL
SOP-20 pin (JEITA)
PRSP0020DD-B...
