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Honeywell International Electronic Components Datasheet

HX6256 Datasheet

32K x 8 Static RAM

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HX6256
32K x 8 Static RAM
The 32K x 8 Radiation Hardened Static RAM is a high performance 32,768
word x 8-bit static random access memory with industry-standard
functionality. It is fabricated with Honeywell’s radiation hardened
technology, and is designed for use in systems operating in radiation
environments. The RAM operates over the full military temperature range
and requires only a single 5 V ± 10% power supply. The RAM is available
www.DatawShitehet4eUit.hceomr TTL or CMOS compatible I/O. Power consumption is typically
less than 15 mW/MHz in operation, and less than 5 mW when de-selected.
The RAM read operation is fully asynchronous, with an associated typical
access time of 17 ns at 5 V.
Honeywell’s enhanced SOI RICMOS™ IV (Radiation Insensitive CMOS)
technology is radiation hardened through the use of advanced and
proprietary design, layout, and process hardening techniques. The
RICMOS™ IV process is a 5-volt, SOI CMOS technology with a 150 Å gate oxide and a minimum drawn feature size of
0.75 µm (0.6 µm effective gate length—Leff). Additional features include tungsten via plugs, Honeywell’s proprietary
SHARP planarization process, and a lightly doped drain (LDD) structure for improved short channel reliability. A 7
transistor (7T) memory cell is used for superior single event upset hardening, while three layer metal power bussing and
the low collection volume SOI substrate provide improved dose rate hardening.
FEATURES
RADIATION
Fabricated with RICMOS™ IV Silicon on Insulator
(SOI) 0.7 µm Process (Leff = 0.6 µm)
Total Dose Hardness through 1x106 rad(SiO2)
Neutron Hardness through 1x1014 cm-2
Dynamic and Static Transient Upset Hardness
through 1x109 rad(Si)/s
Dose Rate Survivability through 1x1011 rad(Si)/s
Soft Error Rate of <1x10-10 upsets/bit-day in
Geosynchronous Orbit
No Latchup
OTHER
Listed On SMD#5962–95845
Fast Cycle Times
o 17 ns (Typical)
o 25 ns (-55 to 125°C) Read Write Cycle
Asynchronous Operation
o CMOS or TTL Compatible I/O
Single 5 V ± 10% Power Supply
Packaging Options
o 28-Lead CFP (0.500 in. x 0.720 in.)
o 28-Lead DIP, MIL-STD-1835, CDIP2-T28
o 36-Lead CFP—Bottom Braze (0.630 x 0.650 in.)
o 36-Lead CFP—Top Braze (0.630 x 0.650 in.)


Honeywell International Electronic Components Datasheet

HX6256 Datasheet

32K x 8 Static RAM

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HX6256
FUNCTIONAL DIAGRAM
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SIGNAL DEFINITIONS
A: 0-14 Address input pins which select a particular eight-bit word within the memory array.
DQ: 0-7 Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS
Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables
all input buffers except CE. If this signal is not used it must be connected to VSS.
NWE
Negative write enable, when at a low level activates a write operation and holds the data output drivers in a high
impedance state. When at a high level NWE allows normal read operation.
NOE
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a
low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must be
connected to VSS.
CE* Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
TRUTH TABLE
NCS
CE*
LH
LH
HX
XL
NWE
H
L
XX
XX
NOE
L
X
XX
XX
*Not Available in 28-lead DIP or 28-Lead Flat Pack
MODE
Read
Write
Deselected
Disabled
DQ
Data Out
Data In
High Z
High Z
Notes:
X: VI=VIH or VIL
XX: VSSVIVDD
NOE=H: High Z output state
maintained for NCS=X,
CE=X, NWE=X
2 www.honeywell.com/radhard


Part Number HX6256
Description 32K x 8 Static RAM
Maker Honeywell
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