* JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 4 Bank architecture Posted CAS Programmable CAS Latency 3 , 4 , 5 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination
HYMP512Uxxx Datasheet (442.92 KB)
HYMP512Uxxx
Hynix
442.92 KB
Ddr2 sdram unbuffered dimms based on 512m.
240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb 1st ver. This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 512Mb 1st ver. D.
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