HY5756820LT Datasheet | SK Hynix

.. HY57V56820C(L)T 4 Banks x 8M x 8Bit Synchronous DRAM DESCRIPTION The HY57V56820C is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. The HY57V56820C is organized as 4banks of 8,388,608x8. The HY57V56820C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are patible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3),...