HY5756820CT Datasheet | SK Hynix

DESCRIPTION The HY57V56820C is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. The HY57V56820C is organized as 4banks of 8,388,608x8. The HY57V56820C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are patible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control mand (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate mand or can be interrupted and replaced by a new burst read or write mand on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES - - - Single 3.3±0.3V power supply All device pins are patible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM Internal four banks operation - - - - Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst - - 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks - - ORDERING INFORMATION Part No. HY57V56820CT-6 HY57V56820CT-K HY57V56820CT-H HY57V56820CT-8 HY57V56820CT-P HY57V56820CT-S HY57V56820CLT-6 HY57V56820CLT-K HY57V56820CLT-H HY57V56820CLT-8 HY57V56820CLT-P HY57V56820CLT-S Clock Frequency 166MHz 133MHz 133MHz Power Organization Interface Package Normal 125MHz 100MHz 100MHz 4Banks x 8Mbits x8 166MHz 133MHz 133MHz Low power 125MHz 100MHz 100MHz LVTTL 400mil 54pin TSOP II This document is a general product...