Voltage : VDD, VDDQ 3.3V supply voltage All device pins are compatible with LVTTL interface JEDEC standard 400mil 86pin TSOP-II with 0.5mm of pin pitch.
Auto refresh and self refresh 4096 Refresh cycles / 64ms Programmable Burst Length and Burst Type
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- 1, 2, 4, 8 or full page for Sequential Burst All inputs and outputs referenced to positive edge of DataSheet4U. com system clock - 1, 2, 4 or 8 for.
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HY57V643220D(L/S)T(P) Series 4Banks x 512K x 32bits Synchronous DRAM Document Title
4Bank x 512K x 32bits Synchronous DRAM
Revision History
Revision No. 0.1 0.2 0.3 0.4 Initial Draft Removed Preliminary
1. Updated Output Load Capacitance for Access Time Measurement CL = 30pF in AC OPERATING TEST CONDITION 2. Updated the tolerance zone of the leads and the description of the package type in PACKAGE DIMENSION 1.Corrected : Lead range tolerance (Page : 13)
History
Draft Date May. 2004 July 2004 Sep. 2004 Sep. 2005
Remark Preliminary
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This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Sep.
HY57V643220D Datasheet
