HY5DU28422AT sdram equivalent, 3rd 128m ddr sdram.
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* VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operat.
which requires large memory density and high bandwidth. The Hynix 128Mb DDR SDRAMs offer fully synchronous operations re.
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