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HY5RS573225F Datasheet 256 Gddr3 Sdram

Manufacturer: SK Hynix

Overview: HY5RS573225F www.DataSheet4U.com 256M (8Mx32) GDDR3 SDRAM HY5RS573225F This document is a general.

General Description

and is subject to change without notice.

Hynix Electronics does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • VDD=1.8V ± 0.1V, VDDQ=1.8V ± 0.1V Single ended READ Strobe (RDQS) per byte Single ended WRITE Strobe (WDQS) per byte Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Calibrated output drive Differential clock inputs (CK and CK#) Commands entered on each positive CK edge RDQS edge-aligned with data for READs; with WDQS center-aligned with data for WRITEs Four interna.

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