HY5RS573225F Datasheet | SK Hynix

.. 256M (8Mx32) GDDR3 SDRAM HY5RS573225F This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Apr. 2004 1 HY5RS573225F Revision History Revision No. 0.1 0.2 0.3 0.4 .. History Defined target spec. Full Revision Defined IDD Spec. Insert AC parameter (-12/ -13/ -14/ -15) Draft Date Apr. 2003 Oct. 2003 Dec. 2003 Apr. 2004 Remark Rev. 0.4 / Apr. 2004 HY5RS573225F DESCRIPTION The Hynix HY5RS573225 is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. The Hynix HY5RS573225 is internally configured as a quad-bank DRAM. The Hynix HY5RS573225 uses a double data rate architecture to achieve high-speed opreration. The double date rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the Hynix HY5RS573225 consists of a 4n-bit wide, every two-clock-cycles data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the Hynix HY5RS573225 is burst oriented; accesses start at a selected locations and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE mand, which is then followed by a READ of WRITE mand. The address bits registered coincident with the ACTIVE mand are used to select the bank and row to be accessed (BA0, BA1 select .. the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE mand are used to select the starting column location for the burst access. Prior to normal operation, the Hynix HY5RS573225 must be initialized. Features - - - - - - - - - VDD=1.8V ± 0.1V, VDDQ=1.8V...