* High-speed access time: 8, 10, 12, and 15 ns CMOS low power operation TTL and CMOS compatible interface levels Single 3.3V ± 10%power supply Fully static operation: no clock or refresh required
* Three state outputs
* Data control for
IC61LV12816 Datasheet (150.42 KB)
IC61LV12816
ICSI
150.42 KB
128k x 16 hight speed sram.
IC61LV12816 Document Title 128K x 16 Hight Speed SRAM with 3.3V Revision History Revision No 0A 0B 1 Draft Date Remark September 12,2001 April 23,20.
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