lvpecl translator.
* 1 differential 2.5V/3.3V LVPECL output
* LVCMOS/LVTTL CLK input
* CLK accepts the following input levels: LVCMOS or LVTTL
* Maximum output frequency: 26.
where space, high performance and low power are important.
ICS
BLOCK DIAGRAM
CLK Q nQ
PIN ASSIGNMENT
nc Q nQ nc 1 2 3.
The ICS85320I is a LVCMOS / LVTTL-to-Differential 2.5V / 3.3V LVPECL translator and a memHiPerClockS™ ber of the HiPerClocks™family of High Performance Clocks Solutions from ICS. The ICS85320I has a single ended clock input. The single ended clock in.
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