8SLVD1204-33 Description
The 8SLVD1204-33 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD1204-33 is characterized to operate from a 3.3V power supply.
8SLVD1204-33 Key Features
- Four low skew, low additive jitter LVDS output pairs
- Two selectable differential clock input pairs
- Differential PCLKx, nPCLKx pairs can accept the following
- Maximum input clock frequency: 2GHz
- LVCMOS/LVTTL interface levels for the control input select pin
- Output skew: 20ps (maximum)
- Propagation delay: 310ps (maximum)
- L10okwHazd-d2iti0vMe Hphz:a1s0e0jiftste(rm, RaxMimS;ufmR)EF = 156.25MHz, VPP = 1V
- Full 3.3V supply voltage
- Lead-free (RoHS 6), 16-Lead VFQFPN packaging