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ICS854S01I Datasheet

2:1 Differential-to-LVDS Multiplexer

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2:1 Differential-to-LVDS Multiplexer
ICS854S01I
DATASHEET
General Description
The ICS854S01I is a high performance 2:1 Differential-to-LVDS
Multiplexer. The ICS854S01I can also perform differential translation
because the differential inputs accept LVPECL, LVDS or CML levels.
The ICS854S01I is packaged in a small 3mm x 3mm 16 VFQFN
package, making it ideal for use on space constrained boards.
Features
2:1 LVDS MUX
One LVDS output pair
Two differential clock inputs can accept: LVPECL, LVDS, CML
Maximum input/output frequency: 2.5GHz
Translates LVCMOS/LVTTL input signals to LVDS levels by using
a resistor bias network on nPCLK0, nPCLK1
RMS additive phase jitter: 0.06ps (typical)
Propagation delay: 600ps (maximum)
Part-to-part skew: 350ps (maximum)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
CLK_SEL Pulldown
0
Q
nQ
1
Pin Assignment
16 15 14 13
PCLK0 1
12 GND
nPCLK0 2
11 Q
PCLK1 3
10 nQ
nPCLK1 4
9 GND
5 6 78
ICS854S01I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
ICS854S01AKI June 15, 2017
1 ©2017 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

ICS854S01I Datasheet

2:1 Differential-to-LVDS Multiplexer

No Preview Available !

ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3
4
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
Input
Input
Input
Input
Type
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Description
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
5 RESERVED Reserve
Reserve pin.
6
7, 16
8, 13
9, 12, 14, 15
10, 11
CLK_SEL
nc
VDD
GND
nQ, Q
Input
Unused
Power
Power
Output
Pulldown
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When
LOW, selects PCLK0, nPCLK0 inputs. LVCMOS / LVTTL interface levels.
No connects.
Power supply pins.
Power supply ground.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
37
37
Maximum
Units
pF
k
k
Function Tables
Table 3. Control Input Function Table
CLK_SEL
0
PCLK Selected
PCLK0, nPCLK0
1 PCLK1, nPCLK1
ICS854S01AKI June 15, 2017
2 ©2017 Integrated Device Technology, Inc.


Part Number ICS854S01I
Description 2:1 Differential-to-LVDS Multiplexer
Maker IDT
Total Page 17 Pages
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