FEATURES:
• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
• 11 ns typical clock to output
• IOL = 14mA over full military temperature range
• CMOS power levels (5/lW typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than ALS (5/l max.)
• Octal transparent latch with 3-state output
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
DESCRIPTION:
The IDT54/74AHCT533 are octal transparent latches built
using advanced CEMOS··, a dual metal CMOS technology. The
IDT54n4AHCT533 consist of eight latches with 3-state outputs
for bus organized system applications. The flip-flops appear
transparent to the data when Latch Enable (LE) is HIGH. When
LE is LOW, the data that meets the setup times is latched. Data
apJ'ears on the bus when the Output Enable (OE) is LOW. When
OE is HIGH, the bus output is in the high impedance state.
PIN CONFIGURATIONS
OE Vee
o. 0,
D. 0,
0, D.
0, o.
0, Os
0, Os
0, D.
0, 0,
GND
LE
SSD54174FCT533~()()1
DIP
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
D. 0,
0,
0,
D3 D2 02 'Of D1
LJ lJLJ LJLJ
0, ~98 7 6 5 43::
GND :::10
2::
LE :11
1:::::
0, :::12
20:::
"-D.
::1~4
r1
n15
16
r1
17
n
1:9 :::
r1
Os 050606 D1
D.
O.
OE
Vee
0,
SSD54174FCT533-002
LCC
TOPYIEW
Os D. 0,
LE --~~>---4----~~--~----~----4-----~--~----~----4-----~--~----~----4-----~--~
0, 0, 0,
CEMOS is a trademark of Integrated Oevice Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
c 1986 Integrated Device Technology, Inc.
5-76
Os O. 0,
SSDAHCT533-003
JULY 1986
Printed in U.S.A.
