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IDT71V67903 - 3.3V Synchronous SRAMs

Download the IDT71V67903 datasheet PDF. This datasheet also covers the IDT71V67703 variant, as both devices belong to the same 3.3v synchronous srams family and are provided as variant models within a single manufacturer datasheet.

Description

The IDT71V67703/7903 are high-speed SRAMs organized as 256K x 36/512K x 18.

data, address and control registers.

There are no registers in the data output path (flow-through architecture).

Features

  • x x x x x x x x 256K x 36, 512K x 18 memory configurations Supports fast access times:.
  • 7.5ns up to 117MHz clock frequency.
  • 8.0ns up to 100MHz clock frequency.
  • 8.5ns up to 87MHz clock frequency LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 3.3V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin thin p.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT71V67703_IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT71V67903
Manufacturer IDT
File Size 168.60 KB
Description 3.3V Synchronous SRAMs
Datasheet download datasheet IDT71V67903 Datasheet

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Other Datasheets by IDT

Part Number Description
IDT71V67902 (IDT71V67702 / IDT71V67902) Burst Counter Flow-Through Outputs / Single Cycle Deselect
IDT71V67603 3.3V Synchronous SRAMs
IDT71V67603Z 3.3V Synchronous SRAMs
IDT71V67702 (IDT71V67702 / IDT71V67902) Burst Counter Flow-Through Outputs / Single Cycle Deselect
IDT71V67703 3.3V Synchronous SRAMs

Full PDF Text Transcription

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www.DataSheet4U.com 256K X 36, 512K X 18 IDT71V67703 3.3V Synchronous SRAMs IDT71V67903 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect Features x x x x x x x x 256K x 36, 512K x 18 memory configurations Supports fast access times: – 7.5ns up to 117MHz clock frequency – 8.0ns up to 100MHz clock frequency – 8.5ns up to 87MHz clock frequency LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 3.3V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin thin plastic quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA).
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