IS43DR32801A
Description
ISSI's 256Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation.
Key Features
- Double data rate interface: two data transfers per clock cycle
- Differential data strobe (DQS, DQS)
- 4-bit prefetch architecture
- On chip DLL to align DQ and DQS transitions with CK
- 4 internal banks for concurrent operation
- Programmable CAS latency (CL) 3, 4, 5, and 6 supported
- Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, and 5 supported
- WRITE latency = READ latency - 1 tCK
- Adjustable data-output drive strength, full and reduced strength options
- On-die termination (ODT)
