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IS46DR82560C Datasheet Ddr2 Dram

Manufacturer: ISSI (now Infineon)

Overview: IS43/46DR82560C IS43/46DR16128C 256Mx8, 128Mx16 DDR2 DRAM.

General Description

ISSI's 2Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation.

The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.

ADDRESS TABLE Parameter 256M x 8 128M x 16 Configuration 32M x 8 x 8 16M x 16 x 8 banks banks Refresh Count 8K/64ms 8K/64ms Row Addressing 32K (A0-A14) 16K (A0-A13) Column Addressing 1K (A0-A9) 1K (A0-A9) Bank Addressing BA0-BA2 BA0-BA2 Precharge A10 A10 Addressing KEY TIMING PARAMETERS Speed Grade -25D -3D tRCD 12.5 15 tRP 12.5 15 tRC 55 55 tRAS 40 40 tCK @CL=3 5 5 tCK @CL=4 3.75 3.75 tCK @CL=5 2.5 3 tCK @CL=6 2.5 — Copyright © 2016 Integrated Silicon Solution, Inc.

Key Features

  • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V.
  • JEDEC standard 1.8V I/O (SSTL_18-compatible).
  • Double data rate interface: two data transfers per clock cycle.
  • Differential data strobe (DQS, DQS).
  • 4-bit prefetch architecture.
  • On chip DLL to align DQ and DQS transitions with CK.
  • 8 internal banks for concurrent operation.
  • Programmable CAS latency (CL) 3, 4, 5, 6, and 7 supported.
  • Posted CAS and programmable additive latency (AL).

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