IS61DDPB22M36C1 Datasheet | ISSI

Features - 2Mx36 and 4Mx18 configuration available. - mon I/O read and write ports. - Max. 567 MHz clock for high bandwidth - Synchronous pipeline read with self-timed late write operation. - Double Data Rate (DDR) interface for read and write input ports. - 2.5 cycle read latency. - Fixed 2-bit burst for read and write operations. - Two input clocks (K and K#) for address and control registering at rising edges only. - Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. - +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. - HSTL input and output interface. - Full data coherency. - On-chip Delay-Locked Loop (DLL) for wide data valid window. - Boundary scan using limited set of JTAG 1149.1 functions. - Byte write capability. - Fine ball grid array (FBGA) package: 13mm x 15mm & 15mm x 17mm body size 165-ball (11 x 15) array - Programmable impedance output drivers via 5x user-supplied precision resistor. - Data Valid Pin (QVLD). - ODT (On Die Termination) feature is supported optionally on data input, K/K#, and BWx#. - The end of top mark (C/C1/C2) is to define options. IS61DDPB22M36C : Don’t care ODT function and pin connection IS61DDPB22M36C1 : Option1 IS61DDPB22M36C2 : Option2 Refer to more detail description at page 6 for each ODT option. DESCRIPTION The 72Mb IS61DDPB22M36C/C1/C2 and IS61DDPB24M18 C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a mon I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-IIP (Burst of 2) CIO SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer...