IS61NLP51218A equivalent, 9mb state bus sram .
* 100 percent bus utilization
* No wait cycles between Read and Write
* Internal self-timed write cycle
* Individual Byte Write Control
* Single R/W (.
They are organized as 256K words by 36 bits and 512K words by 18
bits, fabricated with ISSI's advanced CMOS technology.
Image gallery
Download