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IS61NVF25672 Datasheet State Bus Sram

Manufacturer: ISSI (now Infineon)

Overview: IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418  256K x 72, 512K x 36 and 1M x 18 NOVEMBER 2013 18Mb, FLOW THROUGH 'NO WAIT' STATE BUS.

This datasheet includes multiple variants, all published together in a single manufacturer document.

General Description

• 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single Read/Write control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 165-ball PBGA and 209- ball (x72) PBGA packages • Power supply: NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) • JTAG Boundary Scan for PBGA packages • Industrial temperature available • Lead-free available The 18 Meg 'NLF/NVF' product family

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More Datasheets from ISSI (now Infineon)

Part Number Description
IS61NVF25618A (IS61NVFxxxxxA) STATE BUS SRAM
IS61NVF25636A (IS61NVFxxxxxA) STATE BUS SRAM
IS61NVF204818A 36Mb STATE BUS SRAM
IS61NVF102436A 36Mb STATE BUS SRAM
IS61NVF12836A (IS61NVFxxxxxA) STATE BUS SRAM
IS61NVF51218A (IS61NVFxxxxxA) STATE BUS SRAM
IS61NVP10018 (IS61NVP10018 / IS61NVP51236) State Bus SRAM
IS61NVP102418 (IS61NVPxxxxx) STATE BUS SRAM
IS61NVP102418B 18Mb STATE BUS SYNCHRONOUS SRAM
IS61NVP12818A (IS61NVPxxxxxA) STATE BUS SRAM