IS61VF102418A Datasheet | ISSI

( Data Sheet : .. ) IS61LF25672A IS61VF25672A IS61LF51236A IS61VF51236A IS61LF102418A IS61VF102418A 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM ISSI AUGUST 2005 ® Features - Internal self-timed write cycle - Individual Byte Write Control and Global Write - Clock controlled, registered address, data and control - Burst sequence control using MODE input - Three chip enable option for simple depth expansion and address pipelining - mon data inputs and data outputs - Auto Power-down during deselect - Single cycle deselect - Snooze MODE for reduced-power standby - JTAG Boundary Scan for PBGA package - Power Supply LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% VF: VDD 2.5V + 5%, VDDQ 2.5V + 5% - JEDEC 100-Pin TQFP, 119-pin PBGA, 209-Ball PBGA and 165-pin PBGA packages. - Lead-free available DESCRIPTION The ISSI IS61LF/VF25672A, IS61LF/VF51236A and IS61LF/VF102418A are high-speed, low-power synchronous static RAMs designed to provide burstable, highperformance memory for munication and networking applications. The IS61LF/VF25672A is organized as 262,144 words by 72 bits. The IS61LF/VF51236A is organized as 524,288 words by 36 bits. The IS61LF/VF102418A is organized as 1,048,576 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE) input bined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one...