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IC42S32202L - 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM

This page provides the datasheet information for the IC42S32202L, a member of the IC42S32202 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM family.

Description

The ICSI IC42S32202 and IC42S32202L is a high-speed CMOS configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK).

Features

  • Concurrent auto www. datasheet4u. com precharge.
  • Clock rate:166/143/125 MHz.
  • Fully synchronous operation.
  • Internal pipelined architecture.
  • Four internal banks (512K x 32bit x 4bank).
  • Programmable Mode -CAS#Latency:2 or 3 -Burst Length:1,2,4,8,or full page -Burst Type:interleaved or linear burst -Burst-Read-Single-Write.
  • Burst stop function.
  • Individual byte controlled by DQM0-3.
  • Auto Refresh and Self Refresh.
  • 4096 refresh cycles/64ms.
  • Single +.

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Datasheet preview – IC42S32202L

Datasheet Details

Part number IC42S32202L
Manufacturer Integrated Circuit Solution
File Size 834.30 KB
Description 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
Datasheet download datasheet IC42S32202L Datasheet
Additional preview pages of the IC42S32202L datasheet.

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Full PDF Text Transcription

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IC42S32202/L Document Title 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM Revision History www.datasheet4u.com Revision No History Initial Draft Draft Date August 17,2004 Remark 0A The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. DR042-0C 08/17/2004 1 IC42S32202/L 512K Words x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES · Concurrent auto www.datasheet4u.
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