IC42S16800L Overview
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All input and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are patible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOP-2. ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product.
IC42S16800L Key Features
- Single 3.3V (± 0.3V) power supply
- Fully synchronous operation referenced to clock rising edge
- Possible to assert random column access in every cycle
- Quad internal banks contorlled by BA0 & BA1 (Bank Select)
- Byte control by LDQM and UDQM for IC42S16800
- Programmable Wrap sequence (Sequential / Interleave)
- Programmable burst length (1, 2, 4, 8 and full page)
- Programmable CAS latency (2 and 3)
- Automatic precharge and controlled precharge
- CBR (Auto) refresh and self refresh