Datasheet Details
| Part number | IC42S32202L |
|---|---|
| Manufacturer | Integrated Circuit Solution |
| File Size | 834.30 KB |
| Description | 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM |
| Datasheet |
 IC42S32202L Datasheet
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General Description
The ICSI IC42S32202 and IC42S32202L is a high-speed CMOS configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK).
Key Features
- Concurrent auto www. datasheet4u. com precharge.
- Clock rate:166/143/125 MHz.
- Fully synchronous operation.
- Internal pipelined architecture.
- Four internal banks (512K x 32bit x 4bank).
- Programmable Mode -CAS#Latency:2 or 3 -Burst Length:1,2,4,8,or full page -Burst Type:interleaved or linear burst -Burst-Read-Single-Write.
- Burst stop function.
- Individual byte controlled by DQM0-3.
- Auto Refresh and Self Refresh.
- 4096 refresh cycles/64ms.
- Single +.