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IC42S32202 Datasheet 512k X 32 Bit X 4 Banks (64-mbit) Sdram

Manufacturer: Integrated Circuit Solution

Overview: IC42S32202/L Document Title 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM Revision History .. Revision No History Initial Draft Draft Date August 17,2004 Remark 0A The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc.

General Description

The ICSI IC42S32202 and IC42S32202L is a high-speed CMOS configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK).

Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits.Read and write accesses start at a selected locations in a programmed sequence.

Accesses begin with the registration of a BankActive mand which is then followed by a Read or Write mand The ICSI IC42S32202 and IC42S32202L provides for programmable Read or Write burst lengths of 1,2,4,8,or full page, with a burst termination operation.

Key Features

  • Concurrent auto www. datasheet4u. com precharge.
  • Clock rate:166/143/125 MHz.
  • Fully synchronous operation.
  • Internal pipelined architecture.
  • Four internal banks (512K x 32bit x 4bank).
  • Programmable Mode -CAS#Latency:2 or 3 -Burst Length:1,2,4,8,or full page -Burst Type:interleaved or linear burst -Burst-Read-Single-Write.
  • Burst stop function.
  • Individual byte controlled by DQM0-3.
  • Auto Refresh and Self Refresh.
  • 4096 refresh cycles/64ms.
  • Single +.

More Datasheets from Integrated Circuit Solution

Part Number Description
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