clock generator.
* 2 divide by 1 differential 3.3V LVPECL outputs; 2 divide by 2 differential 3.3V LVPECL outputs
* Selectable CLK, nCLK or LVPECL clock inputs
* CLK, nCLK pai.
demanding well defined performance and repeatability.
BLOCK DIAGRAM
QA0 nQA0 CLK_EN D Q LE CLK nCLK PCLK nPCLK CLK_SEL .
The ICS8737-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/ HiPerClockS™ Divider and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8737-11 has two selectable clock inputs. The.
Image gallery
TAGS
Manufacturer
Related datasheet