ICS9112-27 Datasheet | Integrated Circuit Systems

Features - - - - - - Frequency range 0 - 140 MHz (3.3V) Less than 200 ps Jitter between outputs Skew controlled outputs < 100 ps Distribute one clock input to one bank of four outputs 3.3V ±10% operation Available in 8 pin TSSOP, and SOIC packages. Block Diagram LOGIC CONTROL CLK0 CLK1 CLK_IN Pin Descriptions PIN NUMBER 1 2 3 4 5 6 7 8 0055G- 04/26/05 w PIN NAME CLK_IN OE CLK0 GND CLK1 VDD CLK2 CLK3 w .D w TYPE IN IN OUT PWR OUT PWR OUT OUT t a CLK2 CLK3 S a e h t e CLK_IN OE 1 2 3 4 CLK0 U 4 Pin Configuration 8 7 6 5 CLK3 CLK2 VDD CLK1 .c m o 8 pin TSSOP & SOIC Functionality Table INPUTS CLK_IN 0 0 1 1 OE 0 1 0 1 OUTPUTS CLK(3:0) Tristate 0 Tristate 1 DESCRIPTION Input reference frequency. Output enable. When OE is low, it tristates the clock outputs Buffered clock output Ground Buffered clock output Power supply for 3.3V Buffered clock output Buffered clock output w w w .D a S a t e e h U 4 t m o .c Absolute Maximum Ratings Supply voltage range VDD - - - - - - -0.5V to 4.3 V Input voltage range VI (see notes 1 & 2) - . . . -0.5V to VDD + 0.5V Output voltage range VO (see notes 1 &...