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ICS952011 - Programmable Timing Control Hub

Description

The ICS952011 is a two chip clock solution for desktop designs using SIS 645/645DX/648/650 style chipsets.

When used with a zero delay buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks signals for such a system.

Features

  • 2 - Pairs of differential CPUCLKs (differential current mode).
  • 1 - SDRAM @ 3.3V.
  • 9 - PCI @3.3V (including 2 free-running).
  • 2 - AGP @ 3.3V.
  • 2 - ZCLKs @ 3.3V.
  • 1- 12/48MHZ @ 3.3V.
  • 1- 24/48MHz, @3.3V selectable by I2C.
  • 3- REF @3.3V, 14.318MHz. Key Specifications:.
  • PCI - PCI output skew: < 500ps.
  • CPU - SDRAM output skew: < 1ns.
  • AGP - AGP output skew:.

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Datasheet preview – ICS952011

Datasheet Details

Part number ICS952011
Manufacturer Integrated Circuit Systems
File Size 368.64 KB
Description Programmable Timing Control Hub
Datasheet download datasheet ICS952011 Datasheet
Additional preview pages of the ICS952011 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS952011 Programmable Timing Control Hub™ for P4™ processor Recommended Application: SIS 645/645DX/648/650 style chipsets. Output Features: • 2 - Pairs of differential CPUCLKs (differential current mode) • 1 - SDRAM @ 3.3V • 9 - PCI @3.3V (including 2 free-running) • 2 - AGP @ 3.3V • 2 - ZCLKs @ 3.3V • 1- 12/48MHZ @ 3.3V • 1- 24/48MHz, @3.3V selectable by I2C • 3- REF @3.3V, 14.318MHz. Key Specifications: • PCI - PCI output skew: < 500ps • CPU - SDRAM output skew: < 1ns • AGP - AGP output skew: <150ps Features/Benefits: • Selectable asynchronous/synchronous AGP, ZCLK and PCI outputs • Supports DDR333 OEM frequencies • Programmable output frequency, divider ratios, output rise/falltime, output skew.
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