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Integrated Circuit Systems
Integrated Circuit Systems

ICS9DB401 Datasheet Preview

ICS9DB401 Datasheet

Four Output Differential Buffer

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ICS9DB401 pdf
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Integrated
Circuit
Systems, Inc.
Four Output Differential Buffer for PCI Express
ICS9DB401
Recommended Application:
DB800 Version 2.0 Yellow Cover part with PCI Express
support with extended bypass mode frequency range.
Output Features:
• 4 - 0.7V current-mode differential output pairs
• Supports zero delay buffer mode and fanout mode
• Bandwidth programming available
Key Specifications:
• Outputs cycle-cycle jitter: < 50ps
• Outputs skew: < 50ps
• Extended frequency range in bypass mode:
Revision B: up to 333.33MHz
Revision C: up to 400MHz
Features/Benefits:
• Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
• Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
Pin Configurations
VDD 1
SRC_IN 2
SRC_IN# 3
GND 4
VDD 5
DIF_1 6
DIF_1# 7
OE_1 8
DIF_2 9
DIF_2# 10
VDD 11
BYPASS#/PLL 12
SCLK 13
SDATA 14
OE_INV = 0
VDD 1
SRC_IN 2
SRC_IN# 3
GND 4
VDD 5
DIF_1 6
DIF_1# 7
OE1# 8
DIF_2 9
DIF_2# 10
VDD 11
BYPASS#/PLL 12
SCLK 13
SDATA 14
OE_INV = 1
28 VDDA
27 GNDA
26 IREF
25 OE_INV
24 VDD
23 DIF_6
22 DIF_6#
21 OE_6
20 DIF_5
19 DIF_5#
18 VDD
17 HIGH_BW#
16 SRC_STOP#
15 PD#
28 VDDA
27 GNDA
26 IREF
25 OE_INV
24 VDD
23 DIF_6
22 DIF_6#
21 OE6#
20 DIF_5
19 DIF_5#
18 VDD
17 HIGH_BW#
16 SRC_STOP
15 PD
28-pin SSOP & TSSOP
1014B—09/07/06
DataSheet4 U .com



Integrated Circuit Systems
Integrated Circuit Systems

ICS9DB401 Datasheet Preview

ICS9DB401 Datasheet

Four Output Differential Buffer

No Preview Available !

ICS9DB401 pdf
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS9DB401
Pin Decription When OE_INV = 0
PIN # PIN NAME PIN TYPE
DESCRIPTION
1 VDD
2 SRC_IN
3 SRC_IN#
4 GND
5 VDD
6 DIF_1
7 DIF_1#
8 OE_1
9 DIF_2
10 DIF_2#
11 VDD
12 BYPASS#/PLL
13 SCLK
14 SDATA
15 PD#
PWR
IN
IN
PWR
PWR
OUT
OUT
IN
OUT
OUT
PWR
IN
IN
I/O
IN
Power supply, nominal 3.3V
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Asynchronous active low input pin used to power down the device. The
internal clocks are disabled and the VCO and the crystal are stopped.
16 SRC_STOP#
17 HIGH_BW#
18 VDD
19 DIF_5#
20 DIF_5
21 OE_6
22 DIF_6#
23 DIF_6
24 VDD
25 OE_INV
26 IREF
27 GNDA
28 VDDA
IN
IN
PWR
OUT
OUT
IN
OUT
OUT
PWR
IN
OUT
PWR
PWR
Active low input to stop SRC outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
1014B—09/07/06
DataSheet4 U .com
2


Part Number ICS9DB401
Description Four Output Differential Buffer
Maker Integrated Circuit Systems
Total Page 16 Pages
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