ddr 24-bit to 48-bit registered buffer.
* Differential clock signals
* Supports SSTL_2 class II specifications on inputs and outputs
* Low-voltage operation - VDD = 2.3V to 2.7V
* Available in .
The 24-bit-to-48-bit ICSSSTV32852 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/ O levels, except for the LVCMOS RESET# input. Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control sig.
Image gallery
TAGS
Manufacturer
Related datasheet
Download (Size : 146.82KB)