* Differential clock signals
* Supports SSTL_2 class II specifications on inputs and outputs
* Low-voltage operation - VDD = 2.3V to 2.7V
* Available in 114 ball BGA package. Pin Configuration 1 A B C D E F G H J 2 3 4 5 6 Truth Table RESET# L H H H Notes: 1. 1 K
ICSSSTV32852 Datasheet (146.82 KB)
ICSSSTV32852
Integrated Circuit Systems
146.82 KB
Ddr 24-bit to 48-bit registered buffer.
Integrated Circuit Systems, Inc. ICSSSTV32852 www.DataSheet4U.com DDR 24-Bit to 48-Bit Registered Buffer Recommended Application: DDR Memo.
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