* Differential clock signals
* Meets SSTL_2 signal data
* Supports SSTL_2 class I specifications on outputs
* Low-voltage operation - VDD = 2.3V to 2.7V
* Available in 64 pin TSSOP and 56 pin MLF packages Pin Configurations Q13A Q12A Q11A Q10A Q9A VDDQ GND Q
ICSSSTVF16859 Datasheet (187.57 KB)
ICSSSTVF16859
Integrated Circuit Systems
187.57 KB
Ddr 13-bit to 26-bit registered buffer.
Integrated Circuit Systems, Inc. ICSSSTVF16859 Advance Information DDR 13-Bit to 26-Bit Registered Buffer Recommended Applications: DDR Me.
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