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ICSSSTV32852 Datasheet - Integrated Circuit Systems

ICSSSTV32852 DDR 24-Bit to 48-Bit Registered Buffer

The 24-bit-to-48-bit ICSSSTV32852 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/ O levels, except for the LVCMOS RESET# input. Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge of CLK is used to .

ICSSSTV32852 Features

* Differential clock signals

* Supports SSTL_2 class II specifications on inputs and outputs

* Low-voltage operation - VDD = 2.3V to 2.7V

* Available in 114 ball BGA package. Pin Configuration 1 A B C D E F G H J 2 3 4 5 6 Truth Table RESET# L H H H Notes: 1. 1 K

ICSSSTV32852_IntegratedCircuitSystems.pdf

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Datasheet Details

Part number:

ICSSSTV32852

Manufacturer:

Integrated Circuit Systems

File Size:

146.82 KB

Description:

Ddr 24-bit to 48-bit registered buffer.

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ICSSSTV32852 ICSSSTV32852 DDR 24-Bit 48-Bit Registered Buffer Integrated Circuit Systems

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