ICSSSTUA32S869B Datasheet - ICS

ICSSSTUA32S869B 14-Bit Configurable Registered Buffer

The ICSSSTUA32S869B is 14-bit 1:2 registered buffer with parity is designed for 1.7 V to 1.9 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers optimized to drive the DDR2 DIMM load. They pr.

ICSSSTUA32S869B Features

* 14-bit 1:2 registered buffer with parity check functionality

* Supports SSTL_18 JEDEC specification on data inputs and outputs

* 50% more dynamic driver strength than standard SSTU32864

* Supports LVCMOS switching levels on C1 and RESET# inputs

* Low voltag

ICSSSTUA32S869B_ICS.pdf