ICSSSTUB32872A Datasheet - ICS

ICSSSTUB32872A 28-Bit Registered Buffer

This 28-bit 1:1 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The ICSSSTUB.

ICSSSTUB32872A Features

* 28-bit 1:1 registered buffer with parity check functionality

* Supports SSTL_18 JEDEC specification on data inputs and outputs

* Supports LVCMOS switching levels on RESET input

* 50% more dynamic driver strength than standard SSTU32864

* Low voltage operati

ICSSSTUB32872A Datasheet (238.50 KB)