ICSSSTUB32871A Datasheet - ICS

ICSSSTUB32871A 27-Bit Registered Buffer

This 27-bit 1:1 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The ICSSSTUB.

ICSSSTUB32871A Features

* 27-bit 1:1 registered buffer with parity check functionality

* Supports SSTL_18 JEDEC specification on data inputs and outputs

* Supports LVCMOS switching levels on RESET input

* 50% more dynamic driver strength than standard SSTU32864

* Low voltage operati

ICSSSTUB32871A Datasheet (228.67 KB)