ICSSSTUAF32868A Datasheet - IDT

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER

This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits opti.

ICSSSTUAF32868A Features

* 28-bit 1:2 registered buffer with parity check functionality

* Supports SSTL_18 JEDEC specification on data inputs and outputs Applications

* DDR2 Memory Modules

* Provides complete DDR DIMM solution with ICS98ULPA877A or IDTCSPUA877A

* Supports LVCMOS swi

ICSSSTUAF32868A_IDT.pdf