ICSSSTUAF32866B Datasheet - IDT

ICSSSTUAF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM.

ICSSSTUAF32866B Features

* 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check functionality

* Supports SSTL_18 JEDEC specification on data inputs and outputs

* Supports LVCMOS switching levels on C0, C1, and RESET inputs

* Low voltage operation: VDD = 1.7V to 1.9V

* Avail

ICSSSTUAF32866B_IDT.pdf