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ICSSSTUAF32865A

25-BIT CONFIGURABLE REGISTERED BUFFER

ICSSSTUAF32865A Features

* 28-bit 1:2 registered buffer with parity check functionality

* Supports SSTL_18 JEDEC specification on data inputs

* and outputs Supports LVCMOS switching levels on CSGateEN and RESET inputs Low voltage operation: VDD = 1.7V to 1.9V Available in 160-ball

ICSSSTUAF32865A General Description

This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The IDT74SST.

ICSSSTUAF32865A Datasheet (453.17 KB)

Preview of ICSSSTUAF32865A PDF

Datasheet Details

Part number:

ICSSSTUAF32865A

Manufacturer:

IDT

File Size:

453.17 KB

Description:

25-bit configurable registered buffer.
www.DataSheet4U.com DATASHEET 28-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTUBF32865A The IDT74SSTUBF32865A includes a parity checking function..

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ICSSSTUAF32865A 25-BIT CONFIGURABLE REGISTERED BUFFER IDT

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