ICSSSTUF32864A Datasheet - Integrated Circuit Systems

ICSSSTUF32864A 25-Bit Configurable Registered Buffer for DDR2

1:2 Register B (C0 = 1, C1 = 1) This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been .

ICSSSTUF32864A Features

* 25-bit 1:1 or 14-bit 1:2 configurable registered buffer

* Supports SSTL_18 JEDEC specification on data inputs and outputs

* Supports LVCMOS switching levels on C0, C1 and RESET# inputs

* Low voltage operation VDD = 1.7V to 1.9V

* Available in 96 BGA package

ICSSSTUF32864A Datasheet (111.62 KB)