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IDT2309A Datasheet

3.3V ZERO DELAY CLOCK BUFFER

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IDT2309A
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY
CLOCK BUFFER
IDT2309A
FEATURES:
• Phase-Lock Loop Clock Distribution
• 10MHz to 133MHz operating frequency
• Distributes one clock input to one bank of five and one bank of
four outputs
• Separate output enable for each output bank
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• IDT2309A-1 for Standard Drive
• IDT2309A-1H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Available in SOIC and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT2309A is a 16-pin version of the IDT2305A. The IDT2309A
accepts one reference input, and drives two banks of four low skew clocks.
The -1H version of this device operates up to 133MHz frequency and has
higher drive than the -1 device. All parts have on-chip PLLs which lock
to an input clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad. In the absence of an input clock, the
IDT2309A enters power down. In this mode, the device will draw less than
12µA for Commercial Temperature range and less than 25µA for Industrial
temperature range, and the outputs are tri-stated.
The IDT2309A is characterized for both Industrial and Commercial
operation.
1
REF
PLL
16 CLKOUT
2 CLKA1
3 CLKA2
14 CLKA3
15
CLKA4
S2 8
S1 9
Control
Logic
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL
c 2004 Integrated Device Technology, Inc.
TEMPERATURE
1
RANGES
6 CLKB1
7 CLKB2
10 CLKB3
11 CLKB4
JULY 2004
DSC - 6588/4


Integrated Device Technology Electronic Components Datasheet

IDT2309A Datasheet

3.3V ZERO DELAY CLOCK BUFFER

No Preview Available !

IDT2309A
3.3V ZERO DELAY CLOCK BUFFER
PIN CONFIGURATION
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16 CLKOUT
15 CLKA4
14 CLKA3
13 VDD
12 GND
11 CLKB4
10 CLKB3
9 S1
SOIC/ TSSOP
TOP VIEW
APPLICATIONS:
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Max. Unit
VDD
Supply Voltage Range
–0.5 to +4.6 V
VI (2)
Input Voltage Range (REF)
–0.5 to +5.5 V
VI
Input Voltage Range
–0.5 to
V
(except REF)
VDD+0.5
IIK (VI < 0)
Input Clamp Current
–50 mA
IO (VO = 0 to VDD) ContinuousOutputCurrent
±50 mA
VDD or GND
Continuous Current
±100 mA
TA = 55°C
Maximum Power Dissipation
0.7
W
(in still air)(3)
TSTG StorageTemperatureRange –65 to +150 °C
Operating
Commercial Temperature
0 to +70 °C
Temperature
Range
Operating
IndustrialTemperature
-40 to +85 °C
Temperature
Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
PIN DESCRIPTION
Pin Name
Pin Number
REF(1)
1
CLKA1(2)
2
CLKA2(2)
3
VDD
GND
4, 13
5, 12
CLKB1(2)
6
CLKB2(2)
7
S2(3)
8
S1(3)
9
CLKB3(2)
10
CLKB4(2)
11
CLKA3(2)
14
CLKA4(2)
15
CLKOUT(2)
16
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
Type Functional Description
IN Input reference clock, 5 Volt tolerant input
Out Output clock for bank A
Out Output clock for bank A
PWR 3.3V Supply
GND Ground
Out Output clock for bank B
Out Output clock for bank B
IN Select input Bit 2
IN Select input Bit 1
Out Output clock for bank B
Out Output clock for bank B
Out Output clock for bank A
Out Output clock for bank A
Out Output clock, internal feedback on this pin
2


Part Number IDT2309A
Description 3.3V ZERO DELAY CLOCK BUFFER
Maker Integrated Device
Total Page 8 Pages
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