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79RC32438 - IDTTM InterpriseTM Integrated Communications Processor

This page provides the datasheet information for the 79RC32438, a member of the 79RC32K438 IDTTM InterpriseTM Integrated Communications Processor family.

Description

for EJTAG/JTAG pins in Table 1.

Changed DDRDM[7:0] from input/output to output only in Tables 1 and 2 and Logic Diagram.

Added new section, Voltage Sense Signal Timing, as part of EJTAG description.

Features

  • 32-bit CPU Core.
  • MIPS32 instruction set.
  • Cache Sizes: 16KB instruction and data caches, 4-Way set associative, cache line locking, non-blocking prefetches.
  • 16 dual-entry JTLB with variable page sizes.
  • 3-entry instruction TLB www. DataSheet4U. com.
  • 3-entry data TLB.
  • Max issue rate of one 32x16 multiply per clock.
  • Max issue rate of one 32x32 multiply every other clock.
  • CPU control with start, stop and single stepping.
  • S.

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Datasheet preview – 79RC32438

Datasheet Details

Part number 79RC32438
Manufacturer Integrated Device Technology
File Size 714.94 KB
Description IDTTM InterpriseTM Integrated Communications Processor
Datasheet download datasheet 79RC32438 Datasheet
Additional preview pages of the 79RC32438 datasheet.

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Full PDF Text Transcription

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IDTTM InterpriseTM Integrated Communications Processor 79RC32438 Features 32-bit CPU Core – MIPS32 instruction set – Cache Sizes: 16KB instruction and data caches, 4-Way set associative, cache line locking, non-blocking prefetches – 16 dual-entry JTLB with variable page sizes – 3-entry instruction TLB www.DataSheet4U.com – 3-entry data TLB – Max issue rate of one 32x16 multiply per clock – Max issue rate of one 32x32 multiply every other clock – CPU control with start, stop and single stepping – Software breakpoints support – Hardware breakpoints on virtual addresses – Enhanced JTAG and ICE Interface that is compatible with v2.
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