QS5917T Datasheet Low Skew CMOS Pll Clock Driver

Manufacturer: Integrated Device Technology

Overview: www.DataSheet.co.kr QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP.

Datasheet Details

Part number	QS5917T
Manufacturer	Integrated Device Technology
File Size	123.95 KB
Description	LOW SKEW CMOS PLL CLOCK DRIVER
Datasheet	QS5917T_IntegratedDeviceTechnology.pdf

General Description

The QS5917T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs.

Eight outputs are available: Q0-Q4, 2xQ, Q/2, Q5.

Careful layout and design insures < 500ps skew between the Q0-Q4, and Q/2 outputs.

Key Features

QS5917T 5V operation 2xQ output, Q/2 output, Q output Outputs tri-state while RST low Internal loop filter RC network Low noise TTL level outputs < 500ps output skew, Q0-Q4 PLL disable feature for low frequency testing Balanced Drive Outputs ± 24mA 132MHz maximum frequency (2xQ output) Functional equivalent to Motorola MC88915 ESD > 2000V Latch-up >.
300mA.

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