QS5917T
FEATURES
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- QS5917T
5V operation 2x Q output, Q/2 output, Q output Outputs tri-state while RST low Internal loop filter RC network Low noise TTL level outputs < 500ps output skew, Q0-Q4 PLL disable feature for low frequency testing Balanced Drive Outputs ± 24m A 132MHz maximum frequency (2x Q output) Functional equivalent to Motorola MC88915 ESD > 2000V Latch-up >
- 300m A Available in QSOP and PLCC packages
DESCRIPTION
The QS5917T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: Q0-Q4, 2x Q, Q/2, Q5. Careful layout and design insures < 500ps skew between the Q0-Q4, and Q/2 outputs. The QS5917T includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external ponents. In addition, TTL level outputs reduce clock signal noise. Various binations of feedback and a divide-by-2 in the VCO path allow applications to be...
