QS532805
FEATURES
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- - JEDEC patible LVTTL level inputs and outputs 10 output, low skew clock signal buffer Monitor output Clock inputs are 5V tolerant Pinout and function patible with QS5805T 25Ω on-chip resistors for low noise Input hysteresis for better noise margin Guaranteed low skew:
- 0.7ns output skew
- 0.7ns pulse skew
- 1ns part-to-part skew Std., A, and B speed grades (B speed in QSOP package only) Available in QSOP and SOIC packages
QS532805/A/B
DESCRIPTION
The QS532805 clock buffer/driver circuits can be used for clock buffering schemes where low skew is a key parameter. This device offers two banks of 5 non-inverting outputs. The QS532805 incorporates 25 Ω series termination resistors. This clock buffer product is designed for use in high performance workstations, embedded and personal puting systems using 3V to 3.6V supply voltages. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. The...
