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QS532807 - GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER

General Description

The QS532807 clock driver/buffer circuit can be used for clock buffering schemes where low skew is a key parameter.

The QS532807 offers ten non-inverting outputs.

Key Features

  • JEDEC compatible LVTTL level 10 low skew clock outputs Clock input is 5V tolerant Pinout and function compatible with QS5807 25Ω on-chip resistors available for low noise Input hysteresis for better noise margin Guaranteed low skew:.
  • 0.35ns output skew (same bank).
  • 0.6ns output skew (different bank).
  • 0.75ns part-to-part skew Available in QSOP and SOIC packages QS532807.

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Datasheet Details

Part number QS532807
Manufacturer Integrated Device Technology
File Size 95.04 KB
Description GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
Datasheet download datasheet QS532807 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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QS532807 3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER FEATURES: − − − − − − − JEDEC compatible LVTTL level 10 low skew clock outputs Clock input is 5V tolerant Pinout and function compatible with QS5807 25Ω on-chip resistors available for low noise Input hysteresis for better noise margin Guaranteed low skew: • 0.35ns output skew (same bank) • 0.6ns output skew (different bank) • 0.75ns part-to-part skew Available in QSOP and SOIC packages QS532807 DESCRIPTION: The QS532807 clock driver/buffer circuit can be used for clock buffering schemes where low skew is a key parameter. The QS532807 offers ten non-inverting outputs.