QS532807 Description
The QS532807 clock driver/buffer circuit can be used for clock buffering schemes where low skew is a key parameter. The QS532807 offers ten non-inverting outputs. Designed in IDT's proprietary QCMOS process, these devices provide low propagation delay buffering with onchip skew of 0.35ns for same-transition, same bank signals.
QS532807 Key Features
- JEDEC patible LVTTL level 10 low skew clock outputs Clock input is 5V tolerant Pinout and function patible with QS5807 2
- 0.35ns output skew (same bank)
- 0.6ns output skew (different bank)
- 0.75ns part-to-part skew Available in QSOP and SOIC packages
- FUNCTIONAL BLOCK DIAGRAM