QS532806A Overview
The QS532806 clock driver/buffer circuit can be used for clock buffering schemes where low skew is a key parameter. The QS532806 offers two banks of five inverting outputs. Designed in IDT's proprietary CMOS process, these devices provide low propagation delay buffering with onchip skew of 0.7ns for same-transition, same-bank signals.
QS532806A Key Features
- JEDEC patible LVTTL level 10 low skew clock outputs Monitor output Clock inputs are 5V tolerant Pinout and function pati
- 0.7ns output skew (same bank)
- 0.9ns output skew (different bank)
- 1ns part-to-part skew Std. and A speed grades Available in QSOP and SOIC packages