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QS532805A - GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER

Download the QS532805A datasheet PDF. This datasheet also covers the QS532805 variant, as both devices belong to the same guaranteed low skew 3.3v cmos clock driver/buffer family and are provided as variant models within a single manufacturer datasheet.

General Description

The QS532805 clock buffer/driver circuits can be used for clock buffering schemes where low skew is a key parameter.

This device offers two banks of 5 non-inverting outputs.

The QS532805 incorporates 25 Ω series termination resistors.

Key Features

  • JEDEC compatible LVTTL level inputs and outputs 10 output, low skew clock signal buffer Monitor output Clock inputs are 5V tolerant Pinout and function compatible with QS5805T 25Ω on-chip resistors for low noise Input hysteresis for better noise margin Guaranteed low skew:.
  • 0.7ns output skew.
  • 0.7ns pulse skew.
  • 1ns part-to-part skew Std. , A, and B speed grades (B speed in QSOP package only).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (QS532805_IntegratedDeviceTechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number QS532805A
Manufacturer Integrated Device Technology
File Size 109.30 KB
Description GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
Datasheet download datasheet QS532805A Datasheet

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Other Datasheets by Integrated Device Technology

Part Number Description
QS532805 GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
QS532805B GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
QS532806 Guaranteed Low Skew 3.3V CMOS Clock Driver/buffer
QS532806A Guaranteed Low Skew 3.3V CMOS Clock Driver/buffer
QS532807 GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
QS532805/A/B GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER FEATURES: − − − − − − − − JEDEC compatible LVTTL level inputs and outputs 10 output, low skew clock signal buffer Monitor output Clock inputs are 5V tolerant Pinout and function compatible with QS5805T 25Ω on-chip resistors for low noise Input hysteresis for better noise margin Guaranteed low skew: • 0.7ns output skew • 0.7ns pulse skew • 1ns part-to-part skew Std., A, and B speed grades (B speed in QSOP package only) Available in QSOP and SOIC packages QS532805/A/B DESCRIPTION The QS532805 clock buffer/driver circuits can be used for clock buffering schemes where low skew is a key parameter.