QS532805B Description
The QS532805 clock buffer/driver circuits can be used for clock buffering schemes where low skew is a key parameter. This device offers two banks of 5 non-inverting outputs. The QS532805 incorporates 25 Ω series termination resistors.
QS532805B Key Features
- JEDEC patible LVTTL level inputs and outputs 10 output, low skew clock signal buffer Monitor output Clock inputs are 5V
- 0.7ns output skew
- 0.7ns pulse skew
- 1ns part-to-part skew Std., A, and B speed grades (B speed in QSOP package only) Available in QSOP and SOIC packages