Integrated Device Technology QS532805B
The QS532805 clock buffer/driver circuits can be used for clock buffering schemes where low skew is a key parameter. This device offers two banks of 5 non-inverting outputs. The QS532805 incorporates 25 Ω series termination resistors.| Part No. | QS532805B |
|---|---|
| Datasheet | QS532805B Download |
| Manufacturer |  Integrated Device Technology |
| Description | GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER |
| Buy | Stock & Price |
FEATURES
: − − − − − − − − JEDEC compatible LVTTL level inputs and outputs 10 output, low skew clock signal buffer Monitor output Clock inputs are 5V tolerant Pinout and function compatible with QS5805T 25Ω on-chip resistors for low noise Input hysteresis for better noise margin Guaranteed low skew:● 0.7ns output skew
● 0.7ns pulse skew
● 1ns part-to-part skew Std., A, and B speed grades (B speed in QSOP package only) Available in QSOP and SOIC packages QS532805/A/B
DESCRIPTION
This clock buffer product is designed for use in high performance workstations, embedded and personal computing systems using 3V to 3.6V supply voltages. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. The QS532805 can accept 5V input and control signals. The QS532805 is characterized for operation at -40°C to +85°C. − − FUNCTIONAL BLOCK DIAGRAM OEA 5 INA OA5 OA1 MON 5 INB OB5 OB1 OEB NOTE: QS532805 has a 25Ω series termination resistor on each clock output, including monitor.
