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QS532806 - Guaranteed Low Skew 3.3V CMOS Clock Driver/buffer

General Description

The QS532806 clock driver/buffer circuit can be used for clock buffering schemes where low skew is a key parameter.

The QS532806 offers two banks of five inverting outputs.

Key Features

  • JEDEC compatible LVTTL level 10 low skew clock outputs Monitor output Clock inputs are 5V tolerant Pinout and function compatible with QS5806 25Ω on-chip resistors for low noise Input hysteresis for better noise margin Guaranteed low skew:.
  • 0.7ns output skew (same bank).
  • 0.9ns output skew (different bank).
  • 1ns part-to-part skew Std. and A speed grades Available in QSOP and SOIC packages Q.

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Datasheet Details

Part number QS532806
Manufacturer Integrated Device Technology
File Size 104.69 KB
Description Guaranteed Low Skew 3.3V CMOS Clock Driver/buffer
Datasheet download datasheet QS532806 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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QS532806/A GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER FEATURES: − − − − − − − − JEDEC compatible LVTTL level 10 low skew clock outputs Monitor output Clock inputs are 5V tolerant Pinout and function compatible with QS5806 25Ω on-chip resistors for low noise Input hysteresis for better noise margin Guaranteed low skew: • 0.7ns output skew (same bank) • 0.9ns output skew (different bank) • 1ns part-to-part skew Std. and A speed grades Available in QSOP and SOIC packages QS532806/A DESCRIPTION The QS532806 clock driver/buffer circuit can be used for clock buffering schemes where low skew is a key parameter. The QS532806 offers two banks of five inverting outputs.