IS61DDB44M18 Datasheet PDF (DDR-II (Burst of 4) CIO Synchronous SRAMs) | Download Integrated Silicon Solution IS61DDB44M18

IS61DDB44M18 - DDR-II (Burst of 4) CIO Synchronous SRAMs

Description

The 72Mb IS61DDB42M36 and IS61DDB44M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Features

2M x 36 or 4M x 18.
On-chip delay-locked loop (DLL) for wide data valid window.
Common I/O read and write ports.
Synchronous pipeline read with late write operation.
Double data rate (DDR-II) interface for read and write input ports.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K) for address and control registering at rising edges only.
Two input clocks (C an.

Datasheet Details

Part number	IS61DDB44M18
Manufacturer	Integrated Silicon Solution
File Size	601.56 KB
Description	DDR-II (Burst of 4) CIO Synchronous SRAMs
Datasheet	IS61DDB44M18 Datasheet
Additional preview pages of the IS61DDB44M18 datasheet.

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Full PDF Text Transcription

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I7D7D2DMR-bII (2M x 36 & 4M x (Burst o. f 4) CIO 18) Synchronous SRAMs A MAY 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common I/O read and write ports. • Synchronous pipeline read with late write operation. • Double data rate (DDR-II) interface for read and write input ports. • Fixed 4-bit burst for read and write operations. • Clock stop support. • Two input clocks (K and K) for address and control registering at rising edges only. • Two input clocks (C and C) for data output control. • Two echo clocks (CQ and CQ) that are delivered simultaneously with data. • +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. • HSTL input and output levels.

Published: Jul 25, 2016 |